SOLUTION
SOLUTION
PFC (Power Factor Correction) topology has high requirements for MOS transistors, with special requirements for temperature rise, efficiency, and system stability. In addition, PFC topology often generates large surge currents during startup, which can reach 5-10 times the normal operating level, especially during repeated switching processes, which poses a more stringent challenge to MOS transistors. Therefore, MOS transistors used in PFC circuits have high requirements for switching characteristics (Ciss), EAS capability, and surge resistance.



SJ-MOS

Product Type

 Package

 Polarity

VDS

VGS

VTH

RDS(on)(Typ.)

RDS(on)

ID(Max.)

IDpulse (Max.)

Ptot

Qg

Ciss

Coss

Crss

(Min.)

(Max.)

(Typ.)

(Max.)

(Max.)

 

 

 

A

A

W

nC

pF

SR60R028S2E

TO-247

N

600V

+/-30V

3.5V

24

28

90

270

425

196

8100

330

1

SR60R040S2E

TO-247

N

600V

+/-30V

3.5V

34

40

67

201

330

137

5600

230

1.2

SR60R043SFD

TO-247

N

600V

+/-30V

4.0V

36

43

64

192

330

140

5600

230

1.2

SR60R075SFD

TO-247

N

600V

+/-30V

4.0V

62

75

41

123

236

78

3200

140

3.7

SR60R099SFD

TO-220F

N

600V

+/-30V

4.0V

80

99

34

136

38

62.5

2960

107

1.5